1. Field of the Invention
The present invention relates to a semiconductor memory device which can hold data during the time when a voltage is not supplied, such as a flash EEPROM (Electronically Erasable and Programmable Read Only Memory) or the like. More particularly, the present invention relates to a semiconductor memory device including a memory cell capable of storing a plurality of data values per cell (multiple bits/cell), such as an MNOS (Metal Nitride Oxide Semiconductor) memory cell.
2. Description of the Background Art
Semiconductor memory devices in which elements are integrated on a semiconductor substrate and data is stored are roughly divided into two type: a volatile semiconductor memory device capable of holding data only during the time when a voltage is supplied; and a semiconductor memory device capable of holding data even during the time when a voltage is not supplied. The two types of semiconductor memory devices are further divided into a plurality of types, depending on the system or the usage.
One of the latter semiconductor memory devices that is most widely used at the present time is a flash EEPROM which allows data to be electrically programmed or erased. A type of flash EEPROM has currently become the mainstream, which has a floating memory cell in which a floating gate whose surface is insulated with oxide film or the like is formed on a channel of a MOS (Metal Oxide Semiconductor) transistor. In the floating memory cell, data is stored by injecting or extracting electrons to/from the floating gate to change a gate voltage threshold value (hereinafter referred to as Vt) at which a source-drain current starts flowing in the MOS transistor.
On the other hand, in recent years, the limelight is shifting again to an MNOS memory cell. Unlike the floating memory cell, the MNOS memory cell has an ONO film formed on the channel of the MOS transistor, and Vt is changed by injecting electrons or holes into a trap of an ONO film interface. The MNOS memory cell is characterized in that trapped static charge (electrons or holes) cannot substantially move. Therefore, in the MNOS memory cell, even if there is an oxide film defect as in the floating memory cell, not all static charge stored therein is extracted. Such a feature possessed by the MNOS memory cell is advantageous with respect to data loss over time (retention problem) which has become more serious in recent years as the thickness of the oxide film is reduced.
In the MNOS memory cell, since the injected static charge does not move, the static charge can be localized on the channel. Generally, the injection of static charge occurs in the vicinity of the drain where hot electrons are generated. Therefore, in the MNOS memory cell, the static charge is localized on the ON film interface in the vicinity of the drain. The source and drain of the MNOS memory cell are determined, depending on a bias condition, and therefore, the bias condition between the source and the drain can be reversed during the time when the semiconductor memory device is used. Therefore, in the MNOS memory cell, two charge localized portions can be formed on both sizes of the channel of the memory cell. Therefore, in the MNOS memory cell, by assigning one piece of data to each of the two charge localized portions, two pieces of data can be stored in one cell. Because of such a feature, expectations are growing for the MNOS memory cell.
FIG. 15A is a cross-sectional diagram illustrating a general MNOS memory cell. In FIG. 15A, on a semiconductor substrate Sub, a LOCOS 101 for element isolation, an ONO film 102, and a gate 103, and a diffusion layer 104 and a diffusion layer 105 below the LOCOS 101, are formed. The gate 103 is generally formed of polysilicon, and when a memory array is configured, is used as a word line. The diffusion layer 104 and the diffusion layer 105 are each the drain or source of a memory cell, and when a memory array is configured, are used as buried bit lines. Charge localized portions 106 and 107 are portions where charge is localized.
FIG. 15B is a schematic diagram illustrating the MNOS memory cell of FIG. 15A. The same reference characters designate the same parts in FIGS. 15A and 15B. Note that, for the sake of simplicity, the gate 103, the diffusion layers 104 and 105 (one is a drain and the other is a source), and the charge localized portions 106 and 107 are indicated with symbols illustrated in FIG. 15B throughout all figures of the accompanying drawings.
FIG. 16 is a schematic diagram illustrating a memory array composed of conventional memory cells and its vicinity. Note that, in FIG. 16, although only a portion of the array is illustrated due to limitations of space, the actual array generally has more memory cells provided vertically and horizontally. As illustrated in FIG. 16, a plurality of memory cells M01 to M06 are arranged in an array extending horizontally in the figure. The gate of each memory cell is connected to a horizontally extending word line WL0 (common node). Specifically, the control gates of the memory cells M01 to M06 are connected to the word line WL0. The source or drain of each memory cell is connected to a corresponding one of vertically extending bit lines BL0 to BL6 (common nodes). For example, the drain or source of the memory cell M01 is connected to the bit line BL0 or BL1, respectively. The drain or source of the memory cell M02 is connected to the bit line BL1 or BL2, respectively.
Each bit line is selectively connected via a switch 108 to one of the inputs of a sense amplifier 109. The drain of a reference cell R01 is connected via a reference bit line RBL to the other input of the sense amplifier 109. The reference cell R01 may be a CMOS transistor which is designed so that a current having substantially a middle magnitude between a memory cell current when held data is 1 and a memory cell current when held data is 0 flows. The reference cell R01 has a source line RSL and a word line RWL. The gate of the reference cell R01 is connected to the word line RWL. An electrode of the reference cell R01 which is not connected to the sense amplifier 109 is a source, which is connected to the source line RSL.
In the case of the conventional example of FIG. 16, when a read operation is performed, a current of each of the memory cells M01 to M06 is compared with a current of the reference cell R01, and data stored in each of the memory cells M01 to M06 is determined, depending on the magnitude relationship of the currents. A memory cell, from which data is read out, is selected by switching the connection of the bit lines to the sense amplifier 109. In this case, when the bit lines are selected, care should be taken when determining from which of the two charge localized portions 106 and 107 of each memory cell data is to be read out.
For example, when static charge stored in the right-hand charge localized portion 107 of the memory cell M02 is read out, the bit line BL1 is connected to the sense amplifier 109, and the bit line BL2 is connected to a ground level. When data is read out from the left-hand charge localized portion 106, the bit line BL2 is connected to the sense amplifier 109, and the bit line BL1 is connected to the ground level. The bit line which is connected to the sense amplifier 109 is precharged to a Hi level immediately before a read operation. Specifically, by reversing the direction of a bias voltage applied to a bit line connected to a memory cell, the source and drain of the memory cell are switched to change the charge localized portions from which data is read.
As described above, two-bit data can be stored in and read from one cell. In some cases, one-bit data is stored in one cell, which may be advantageous in terms of characteristics, reliability, and cost of a product. In this case, a configuration has been proposed in which the opposite charge localized portion of the same cell is normally not used. For example, in the above-described example, only the charge localized portion 107 is used while the use of the charge localized portion 106 is abandoned, so that only one-bit data is stored in one cell. When this memory cell configuration is used, the memory capacity is reduced by half, but this configuration still has superiority over the floating type in terms of the retention problem or the like.
When the MNOS memory cell of FIG. 15A is used to hold one bit per cell, charge is injected into or extracted from only the charge localized portion 107 so as to store data, while charge is not injected into or extracted from the charge localized portion 106, for example. Therefore, the charge localized portion 106 is invariably in a neutral state. When a read operation is performed, a bit line which the switch 108 connects to the sense amplifier 109 in FIG. 16 is a bit line via which data is read out. The bit line used to read out data varies, depending on which of the charge localized portions is used to store data.
FIG. 17 is a schematic diagram illustrating a configuration of a conventional semiconductor memory device, such as a flash memory or the like. The conventional semiconductor memory device comprises memory sectors MS0 to MS3 which are normally used to store data, and a redundant memory sector MS4 which replaces a defective memory sector which occurs due to a problem during a production among the normally used memory sectors. Also, the conventional semiconductor memory device includes a row decoder 110 (X-DEC) which drives a word line common to all the memory sectors including the redundant memory sector MS4, and column decoders 111 to 115 (Y-DECs) and I/O circuits 116 to 120 which are independently provided in the respective memory sectors.
The memory sector is a unit including a group of memory cells. In the case of a flash memory, the memory sector is typically used as a group of memory cells which are simultaneously subjected to an erase operation. Alternatively, the memory sector may be a group of memory cells which have a source line, a bit line, or a word line in common. The row decoder 110 is a group of a decoder which selects one word line in accordance with a designated address and a driver which supplies a potential to the selected word line. Similarly, the column decoders 111 to 115 each select one bit line in accordance with a designated address. Specifically, the column decoder is a group of the switches 108 of FIG. 16. The I/O circuits 116 to 120 are each a circuit group of the sense amplifier 109 and the reference cell R01 of FIG. 16 and a driver and the like.
Next, a conventional redundant relief technique will be described with reference to FIG. 17. When a defective portion is found in the normally used memory sectors MS0 to MS3 during an inspection before shipment of a product, the inspected semiconductor memory device is a defective product if any restoration is not performed. Therefore, by replacing the function of the defective portion thus found with a previously prepared spare portion (redundant memory sector), the semiconductor memory device can be caused to be a non-defective product. This operation is called redundant relief.
For example, assuming that a defect occurs in a memory cell of the memory sector MS1, when the address of the memory sector MS1 is designated, the memory sector MS1 is disabled by changing an access destination to the redundant memory sector MS4. With the above-described configuration, even if a defective portion is present in the memory sector MS1, substantially no problem occurs in actual use, so that the semiconductor memory device can be shipped as a non-defective product (see Japanese Patent Laid-Open Publication No. 05-40702).
The smaller the units in which the redundant relief is performed, the smaller the area which is occupied by prepared redundant memories. Therefore, conventionally, the redundant relief may be performed in units of one word line or one bit line in DRAMs and the like. However, in non-volatile semiconductor memory devices, a defective memory cell often interfere with operations of non-defective memory cells present therearound, and it may be insufficient to perform changing in only the defective memory cell.
For example, in the case of flash memories, even after changing, when an erase operation is performed with respect to a non-defective memory cell, an erase operation is also performed with respect to a defective memory cell at the same time. Therefore, an erase operation with respect to a defective memory cell is repeated along with reprogramming of data, so that the defective memory cell which is in an excessively erased state short-circuits bit lines. In addition, when changing is performed in only a defective memory cell, it is difficult to secure reliability, for example. Therefore, in most flash memories, changing for redundant relief is performed in units of a memory sector (erase unit).
In conventional semiconductor memory devices, according to the above-described method, when a defect occurs in a normally used memory cell (memory sector), the defective memory cell (memory sector) is replaced with a redundant memory cell (redundant memory sector) to perform relief, thereby improving the yield.
The configuration of the memory sector, the row decoder, the column decoder, and the like of FIG. 17 is provided only for illustrative purposes, and various other configurations have been conventionally proposed. Note that all conventional configurations have the following feature in common: a memory cell (memory sector) for redundant relief is provided in addition to a memory cell (memory sector) which is normally used.
However, in the conventional technique, an increase in chip area inevitably occurs, resulting in an increase in chip cost. A significant cost increase cancels a cost reduction due to a yield improvement which is an effect of redundant relief. For example, if a cost increase due to a chip area increase exceeds a cost reduction due to a yield improvement, the redundant relief becomes meaningless. Even if a cost increase due to a chip area increase is smaller than a cost reduction due to a yield improvement, the cost reduction effect due to the yield improvement is diminished, thereby making it difficult to reduce the cost of a product.
The increase of the chip area is also caused by other factors. For example, in semiconductor memory devices, if reprogramming of data is frequently performed, stress during use degrades characteristics of a bit storing data (endurance degradation), and, in the worst case, the data is lost. Therefore, the following technique (BISR: Built-In Self-Repairing) has been proposed: a counter which counts the number of times of reprogramming of data into a memory cell is provided in a semiconductor memory device to detect a predetermined number of times of reprogramming, or alternatively, the endurance degradation of a memory cell is itself detected, so that data stored in a predetermined memory cell is automatically reprogrammed into another memory cell. However, if a new memory cell is provided in a semiconductor memory device so as to achieve BISR, this leads to an increase in chip area and an increase in chip cost, as in the case of the above-described redundant relief.